1. Field of the Invention
This invention relates to computer systems, and more particularly, to an integrated computer system having a unified system memory and improved bus concurrency.
2. Description of the Relevant Art
Typical computer systems include a central processing unit ("CPU") and system memory coupled to a high-speed system bus. Usually, a bus bridge device is employed to bridge the high-speed system bus to a lower-speed peripheral bus. Normally, slower-speed devices, such as modems, drive controllers, and network interfaces, are located on the low-speed bus. Also, in typical computer systems, a graphics controller is located on the high-speed bus. The graphics controller typically includes its own memory separate from the main system memory. This separate graphics memory is used to store screen image data for display on a monitor. Also typically included in modern computer systems is a DMA controller. The DMA controller allows for the direct transfer of data between system memory on the high-speed bus and peripheral bus devices on the low-speed bus.
Referring now to FIG. 1A, a block diagram of a typical prior art computer system 100 is shown. Computer system 100 includes system memory 112 and CPU 114, both coupled to the high-speed system bus 110. A graphics controller 132 is also coupled to the high-speed system bus 110. Bus bridge 120 couples the high-speed system bus 110 to a low-speed peripheral bus 130. One or more bus devices, such as bus device 134, may be coupled to the low-speed peripheral bus 130. Bus device 134 may be any type of bus device commonly found in computer systems, such as a modem device. Graphics controller 132 is connected to graphics memory 133. Also included in computer system 100 is DMA controller 122, which facilitates data transfers between bus device 134 and system memory 112.
System memory 112 typically comprises DRAM memory operating in fast page mode or extended data out (EDO) mode. System memory 112 stores data operated on by CPU 114. CPU 114 transfers data to and from system memory 112 over high-speed system bus 110. CPU 114 may also transfer data to and from bus device 134 through bus bridge 120. Furthermore, DMA controller 122 allows data to be transferred directly between bus device 134 and system memory 112.
Graphics controller 132 operates on data contained in graphics memory 133, which is memory separate from system memory 112. Graphics memory 133 is typically high-speed DRAM or VRAM memory. Graphics memory 133 contains data corresponding to the screen image displayed upon an external monitor. CPU 114 may also access graphics memory 133. However, graphics controller 132 only accesses graphics memory 133 and does not access system memory 112. Graphics controller 132 displays screen images by reading the screen image data stored in graphics memory 133 and converting the screen image data into analog monitor signals which create the screen image display on an external monitor.
An increasingly popular application of computer systems is in small hand-held, low-power, and low-cost computer devices. Thus, it is desirable to have a low-cost, low-power computer system that can be implemented in a small amount of space. One method of obtaining low cost, low power, small sized computer systems is to integrate as many of the computer system functions onto a single integrated circuit device as possible. Technological improvements in the feature size of integrated circuits in recent years have allowed many of the functions shown in computer system 100 to be integrated onto a single monolithic substrate. For example, CPU 114, bus bridge 120, DMA controller 122 and graphics controller 132 may all be integrated into a single device as shown by the dotted-line enclosure 140 in FIG. 1A.
However, such large scale integration poses serious problems. To achieve the goals of low cost and small space it is desirable to integrate the above listed components into as small an integrated circuit package as possible. However, the number of external connections, or pins, required often mandates that a very large and expensive package must be utilized in order to integrate the above components. For example, an IC device integrating the components enclosed by dotted-line 140 would require separate interfaces to graphics memory 133, to high-speed system bus 110 and system memory 112, and to low-speed bus 130. Providing interfaces to all of these external components will greatly increase the pin count of the integrated circuit device represented by dotted-line 140. Furthermore, separate memory controllers for system memory and graphics memory would be required, increasing the gate count (size) of the IC device. Therefore, in order to reduce the size and pin count of the integrated circuit device, it would be desirable to reduce the number of external data interfaces that must be supported. One solution to this problem is to employ a unified memory for both the main system memory and the graphics memory.
Referring now to FIG. 1B, a block diagram of a prior art computer system 150 utilizing a unified memory for both system memory and graphics memory is illustrated. Computer system 150 includes CPU 114 and unified memory 116, both coupled to high-speed system bus 110. Bus bridge 120 couples high-speed system bus 110 to low-speed peripheral bus 130. A bus device 134 is coupled to the low-speed peripheral bus 130. In contrast to computer system 100 of FIG. 1A, graphics controller 118 of computer system 150 in FIG. 1B is coupled to the high-speed system bus 110. Thus, in computer system 150 the CPU 114 and graphics controller 118 both access data in the unified memory 116. In other words, both CPU data and screen image data are stored in the unified memory 116.
The architecture of computer system 150 allows integration of many of the computer system components into a single integrated device, while requiring fewer external interfaces than the integrated device represented by dotted-line 140 in FIG. 1A. As shown by dotted-line 160 in FIG. 1B the CPU 114, graphics controller 118, bus bridge 120 and DMA controller 122 may all be integrated into a single device requiring external data interfaces only to low-speed bus 130 and to high-speed system bus 110 (system memory 116). By utilizing a unified memory architecture, the separate external interface to graphics memory 133 has been eliminated, thus saving numerous pins on the integrated circuit package. Furthermore, only a single memory controller is needed to interface to the unified system memory 116 as opposed to two memory controllers that would be needed if the CPU and graphics memory were separate. Therefore fewer gates and pins are required in the IC device supporting the unified memory architecture of computer system 150. Thus, a smaller, cheaper package may be used for the device.
However, a significant drawback is associated with the architecture of computer system 150. CPU 114, graphics controller 118, and DMA controller 112 must all share the high-speed system bus 110 in order to access the unified memory 116. Therefore, only one of these devices may access the unified memory 116 at a time. For example, if the CPU is currently performing a burst read operation from the unified memory 116, the graphics controller 118 must wait until the CPU access is completed before the graphics controller 118 may access the unified memory 116. This architecture can lead to serious performance bottlenecks. For example, when graphics controller 118 is performing a screen refresh operation, it must have continuous access to the unified memory 116 during the refresh operation. Otherwise, visible glitches would appear to the user on the external monitor. Therefore, during screen refresh operations the CPU and DMA controller are completely denied access to the unified memory 116, thereby severely impairing overall system performance. Likewise, if the DMA controller is performing a long DMA block transfer over the high-speed system bus 110 to the unified memory 116, the graphics controller 118 may have to wait an extended period of time before being able to perform a new screen refresh operation. If this period of time is too long, noticeable glitches will appear on the monitor to the user.
Therefore, it is desirable to have a computer system architecture which allows the CPU, DMA controller, bus bridge and graphics controller to be integrated into a single low-cost, small-sized device. It is further desired for such an integrated device to have as few as possible external interface connections without sacrificing overall system performance. It is also desirable for such a device to support advanced operating systems such as Windows.RTM. and GEOS.